The invention is generally related to the field of semiconductor device fabrication and more specifically to a method for planarization of isolation structures in integrated circuits.
Chemical-mechanical polishing (CMP) is utilized to planarize the oxide or other material used to fill shallow trenches formed for isolation. The most common approach used for CMP in semiconductor device fabrication is to attach a semiconductor wafer to a carrier (which may or may not rotate) via a mounting pad and polish the exposed surface of the wafer by bringing it into contact with a polishing pad (which is mounted on a rotating or non-rotating platen). The mechanical abrasion between the wafer surface and the polishing pad results in the polishing of the wafer surface. To aid in the polishing and the removal of any particles liberated in this process a slurry can be introduced between the wafer surface and the polishing pad. The slurry will interact with the wafer surface thereby making the wafer more easily polishable and the excess slurry will carry away the materials liberated from the wafer during this polishing step.
To achieve proper isolation between devices in integrated circuits a technique known as Shallow Trench Isolation (STI) is used. In this technique a shallow trench is formed in the silicon surface which is subsequently filled with an insulating material consisting usually of a deposited oxide. This deposited oxide is conformal and will follow the contours of the silicon surface resulting in an oxide film of equal thickness both in the trench and on the silicon surface where the devices are to be fabricated.
In order to achieve a planar surface for subsequent device fabrication, CMP is usually employed to remove to oxide that had formed over the silicon surfaces which will contain devices while leaving the oxide in the trench. These silicon surfaces are distributed non-uniformly across the integrated circuit requiring a process that can accommodate the range of integrated circuit densities and produce a uniform planar surface. This non-uniform distribution of silicon surfaces across an integrated circuit and the typical low selectivities (oxide to nitride) of most CMP silica slurries used for oxide polishing can result in significant dishing in areas that contain large trenches, damage to small isolated silicon surfaces, and incomplete removal of oxide from large silicon areas or arrays. Dummy silicon surfaces can be used to lessen these variations but the across-the-wafer and within-die-fill oxide thickness variations are still very high. Typically, to overcome this variation, a patterned etchback is used to decrease the apparent pattern density by etching back the oxide over the silicon surface leaving only extraneous oxide around the edge of the silicon surface that is readily removed using CMP with a short duration polish. This approach adds significant cost to producing the integrated circuit through the addition of a photolithography patterning level. Hence a method is needed that overcomes the limitations of CMP for STI planarization without the increased cost and complexity of the patterned etchback. This invention provides a method that does not require a patterning step, and can accommodate arbitrary circuit densities.
The instant invention involves a method of forming planar isolation structures for use in integrated circuits.
An embodiment of the instant invention is a method of forming isolation structures in a semiconductor substrate comprising the steps of: etching trenches in said substrate, thereby forming substantially unetched areas of said substrate between said trenches; depositing a fill material that substantially fills said trenches, said fill material having an upper surface; forming a etch barrier on said upper surface of said fill material; removing portions of said etch barrier situated over said substantially unetched areas of said substrate thereby exposing portions of said fill material; removing said exposed portions of said fill material; and planarizing said fill material. Preferably the step of removing said etch barrier using a selective etch process, whereby said selective etch process has a etch barrier etch rate that is greater than a fill material etch rate.
An advantage of the instant invention is forming a planar isolation structure for arbitrary circuit densities using a reduced number of steps.